// clock_ctrl.v

// Generated using ACDS version 14.0 200 at 2018.07.19.10:35:09

`timescale 1 ps / 1 ps
module clock_ctrl (
		input  wire  inclk,  //  altclkctrl_input.inclk
		output wire  outclk  // altclkctrl_output.outclk
	);

	clock_ctrl_altclkctrl_0 altclkctrl_0 (
		.inclk  (inclk),  //  altclkctrl_input.inclk
		.outclk (outclk)  // altclkctrl_output.outclk
	);

endmodule
